Integrated circuits are manufactured by forming discrete semiconductor devices in and over the surfaces of wafers formed of silicon or other suitable materials. A multi-level metallurgical interconnection network is then formed over the devices, contacting their active elements, and wiring them together to create the desired circuits. The wiring layers are formed by depositing an insulating layer over the discrete devices, patterning and etching contact openings into the insulating layer, and then depositing conductive material into the contact openings. A conductive layer is formed over the insulating layer and patterned to form wiring interconnections between the device contacts, thereby creating a first level of basic circuitry. The circuits are further interconnected by additional wiring levels laid out over or within additional insulating layers. The various wiring levels are interconnected by conductive vias that extend through the insulating layers. The conductive vias are produced by first forming via openings in the insulating, or dielectric layers, then filling the via openings with a conductive material. The vias may include high aspect ratios. Depending upon the complexity of the overall integrated circuit, several levels of wiring interconnections may be used.
A method for forming the interconnection layers is the damascene process, whereby openings and trenches comprising an image of the interconnection pattern, are formed in an insulating layer. A metal layer is then deposited into the openings and over the insulating layer. The openings may include high aspect ratios, rendering it difficult to completely fill the openings with the conductive material. The deposited metal is polished back to the insulating layer leaving the metal pattern inlaid within the insulating layer. The polishing back of the metal layer may be accomplished by CMP (chemical mechanical polishing), a relatively old process which has found new application in the planarization of insulating layers and more recently in the damascene process. In single damascene processing, a metal line pattern is generated which connects to subjacent vias or contacts. In dual damascene processing, both vias and contacts and a pattern of interconnection leads are formed by a single metal deposition and CMP. A description of both single and dual damascene processes may be found in Chang, C. Y. and Sze, S. M., “ULSI Technology” McGraw-Hill, New York, (1996), p444-445 and in El-Kareh, B., “Fundamentals of Semiconductor Processing Technologies”, Kluwer, Boston (1995), p563-4.
Deposition of the metal layer can be by PVD (physical vapor deposition) methods such as sputtering or vacuum evaporation, by CVD (chemical vapor deposition), or by ECD (electrochemical deposition). The ECD method involves placing the wafer into an electrolyte solution and electroplating a metal layer onto the wafer surface by applying an electric field between the wafer and the electrolyte solution. The ECD method has been found to be particularly desirable for the deposition of copper, the conductive material that is favored as an interconnect medium in advanced semiconductor devices. The metal layer must be deposited to completely fill the via or other opening to ensure good contact resistance between the metal in the via or other opening, and the superjacent and/or subjacent metal that it contacts. Thin seed layers and/or barrier layers may be formed prior to the electrochemical deposition of the bulk metal layer. The electroplating process itself may include a step for seed protection followed by a via fill step, followed, in turn, by a bulk fill step. Conventionally, the electroplating process employs a current density that continuously increases during these steps. Undesirably, this often yields hollow vias or pull-back at the bottom corners of the via or other openings, however. A graph showing successively increasing current densities in a prior art electroplating process is shown in FIG. 1.
Gilton et.al., U.S. Pat. No. 5,151,168 provides an ECD process wherein current densities of less than 1 milliampere/cm2 are used to deposit copper onto a barrier layer to fill contact and via openings. Such low current densities, although producing good quality copper deposits, would predictably have a very low throughput and be unsuited for production uses.
In the electroplating process, additives such as brighteners and levelers may be added to the electrolyte solution to improve the quality and conformality of the deposited metal layer. Such conformality is especially critical when filling openings with high aspect ratios. Brighteners are additives which adsorb onto regions of low electric field and participate in the charge transfer mechanism of the ECD process. Brighteners improve crystalline quality of the deposited metal film but are consumed by the electrochemical process and must therefore be replenished at the growth front during the ECD. In conventional electroplating processes, brighteners are replenished at the reaction front from the bulk of the electrolyte, by normal diffusion assisted by mechanical agitation of the bath containing the electrolyte solution. However, in the presence of high aspect ratio contact/via openings and trenches typically found in current high density integrated circuits, conventional agitation of the electrolyte solution becomes inadequate for timely replenishment of the depleted brighteners at the bases of the openings and trenches. Replenishment of such additives must then rely on diffusion alone, requiring the reduction of deposition current density and thereby the process throughput. The film quality and throughput of current ECD processes are therefore limited by the mass transfer of additives to the deposition front. An inadequate supply of these additives at the deposition front results in reduced mechanical and electrical quality of the electrodeposited metal layer and poor gap filling, i.e., openings with high aspect ratios may be formed to include hollow portions and/or pull-back at the top corners. As such, the use of various additives does not satisfactorily overcome the various shortcomings of known ECD processes.
It is therefore desirable to provide a metal deposition process that is suitable for damascene processing and includes superior deposition characteristics, including the ability to completely fill openings with high aspect ratios.